ablue said:Hi all:
I need to design a pll with frequency centered at 10MHz, but the rms jitter need to be 25ps, does this spec make sense if implemented in ring oscillator?? I havent hands-on experience on pll, so i dont know whether this is easy or not. any advices are appreciate!!!!
fehler said:I think that ring oscillator like Maneatis' structure could do it. I have ever
designed and measured one, with no more than 10 ps rms jitter at 1 GHz.
Since the frequency is only 10 MHz now, the jitter could be better. But you
need to re-set the current for this cell, mine is a bit large.
ablue said:fehler said:I think that ring oscillator like Maneatis' structure could do it. I have ever
designed and measured one, with no more than 10 ps rms jitter at 1 GHz.
Since the frequency is only 10 MHz now, the jitter could be better. But you
need to re-set the current for this cell, mine is a bit large.
what structure you implement your ring osc. If I use single ended structure, then supply noise will kill the performance , if I use differential structure just like differential pair with resistor load, then the rising edge and falling edge cannot match each other, so the flicker noise will be upconvertered and kill the performance. because Vdd = 1.8V, I cannot play more trick in my ring osc, can you give me some more advice!!
thanks a lot
ablue said:Hi fehler
I have read H C Yang's paper, it is really a good structure, but maybe i still need to design another version which use differential ended circuit,and compare those two , because my pll will be integrated with other circuits and the noise come from supply and substrate will not like that of Yang and will be worse.
Anyway, thanks a lot for you help
ablue said:what about the noise of divider/pfd/filter, do them matters?? If so, how can we get those ?
In this application, I make the bandwidth more high to suppress the noise of vco, because my input reference is assumed clean, does it correct?
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