10MHz Pll with 25ps rms jitter

[ablue]

maneatis

Hi all:
I need to design a pll with frequency centered at 10MHz, but the rms jitter need to be 25ps, does this spec make sense if implemented in ring oscillator?? I havent hands-on experience on pll, so i dont know whether this is easy or not. any advices are appreciate!!!!

 

[Teddy]

It is a feasible thing to do. Depends on what technology you are going to use. a) VCO itself can run at 100MHz if equipped with post divide
I believe that your loop filter and PFD will be way more bigger players than VCO

 

[ablue]

Thanks a lot

I've refered many papers about jitter and phase noise of VCO and placed almost all effords on VCO , and almost forgot the noise from filter and PFD.

how do you consider the noise of supply and substrate?? May the jitter due to supply noise be some order larger than that from thermal noise of devices

 

[lyrix]

I feel this spec. is not easy with ring osilator. To achieve this, supply noise and device noise should both be minimized.

 

[fehler]

Hi all:
I need to design a pll with frequency centered at 10MHz, but the rms jitter need to be 25ps, does this spec make sense if implemented in ring oscillator?? I havent hands-on experience on pll, so i dont know whether this is easy or not. any advices are appreciate!!!!

I think that ring oscillator like Maneatis' structure could do it. I have ever
designed and measured one, with no more than 10 ps rms jitter at 1 GHz.
Since the frequency is only 10 MHz now, the jitter could be better. But you
need to re-set the current for this cell, mine is a bit large.

 

[ablue]

I think that ring oscillator like Maneatis' structure could do it. I have ever
designed and measured one, with no more than 10 ps rms jitter at 1 GHz.
Since the frequency is only 10 MHz now, the jitter could be better. But you
need to re-set the current for this cell, mine is a bit large.

what structure you implement your ring osc. If I use single ended structure, then supply noise will kill the performance , if I use differential structure just like differential pair with resistor load, then the rising edge and falling edge cannot match each other, so the flicker noise will be upconvertered and kill the performance. because Vdd = 1.8V, I cannot play more trick in my ring osc, can you give me some more advice!!

thanks a lot

 

[fehler]

I think that ring oscillator like Maneatis' structure could do it. I have ever
designed and measured one, with no more than 10 ps rms jitter at 1 GHz.
Since the frequency is only 10 MHz now, the jitter could be better. But you
need to re-set the current for this cell, mine is a bit large.

what structure you implement your ring osc. If I use single ended structure, then supply noise will kill the performance , if I use differential structure just like differential pair with resistor load, then the rising edge and falling edge cannot match each other, so the flicker noise will be upconvertered and kill the performance. because Vdd = 1.8V, I cannot play more trick in my ring osc, can you give me some more advice!!

thanks a lot

Hi, could you try Yang's structure then? It is a paper appears in JSSC, the first
author is H C Yang. This vco cell is single ended, but the common mode performance is believed superior.

 

[ablue]

Hi fehler

I have read H C Yang's paper, it is really a good structure, but maybe i still need to design another version which use differential ended circuit,and compare those two , because my pll will be integrated with other circuits and the noise come from supply and substrate will not like that of Yang and will be worse.

Anyway, thanks a lot for you help

 

[fehler]

Hi fehler

I have read H C Yang's paper, it is really a good structure, but maybe i still need to design another version which use differential ended circuit,and compare those two , because my pll will be integrated with other circuits and the noise come from supply and substrate will not like that of Yang and will be worse.

Anyway, thanks a lot for you help

Hi ablue,

I think that the differential version of Yang's vco is Maneatis' vco. For Yang's
vco, the power suppy and substrate noise rejection will be good, I think, which
is demonstrated by Yang's paper. But, you can design one Yang and one Maneatis,
try the make comparisons.

Yang's vco could reject power supply noise, for it use current source in PMOS.
It can reject ground noise for it use symmetric NMOS. But, you need gurentee
local bias for it. And still, you need a best guard ring. I think.

In my idea, they will be similar good for your requirement. But I have not verified
it.

 

[ablue]

what about the noise of divider/pfd/filter, do them matters?? If so, how can we get those ?

In this application, I make the bandwidth more high to suppress the noise of vco, because my input reference is assumed clean, does it correct?

 

[yaxazaa]

Generally speeking, it's good. Rule of thrumb is 5% of the period of the frequency.

 

[fehler]

what about the noise of divider/pfd/filter, do them matters?? If so, how can we get those ?

In this application, I make the bandwidth more high to suppress the noise of vco, because my input reference is assumed clean, does it correct?

I think that divdier will not affect the jitter to much, for it could be taken as a
stage of vco. Then, the total contribution to the jitter will be no more than one
stage's. See Weigandt's thesis.

For pfd, I know nothing.

For lpf, I think that you must take care of the ground noise coupled to the output
node of lpf. For this noise will directedly modulate your vco. I think that carefully
layout could do it.

Then, the most important noise source is the vco itself.

 

[ablue]

If bandwidth of pll is larger than 1/10 of input frequency, what will happen? someone say that this is because of nyquister law(I dont understand), some other say that this is because the model we used is a contiuous time model but in fact pll should be a discrete time system, do these view means same?
sorry I havent enough time to read some text books, so I hope you guys can give me more opnions of yours

 

[xwcwc1234]

I think the 1/10 bandwidth of PLL is due to the discrete nature of PLL loop . Since the analysis is performed on continuous domain , the result should be some difference between the two. The assumption of 1/10 is need for continuous time analysis of PLL .

 

[xwcwc1234]

fehler wrote:


I think that ring oscillator like Maneatis' structure could do it. I have ever
designed and measured one, with no more than 10 ps rms jitter at 1 GHz.
Since the frequency is only 10 MHz now, the jitter could be better. But you
need to re-set the current for this cell, mine is a bit large.


Do you think the maneatis' structure is better than ever ? I read that paper but I don't know whether the jitter of 10 MHz VCO will be smaller than 1GHz or not . As I know low frequency of VCO is more noisy than high frequency , is that true ?

 

[Teddy]

Well it seems thet we are talking about 0.18um CMOS. In this case I would go for differential VCO ring osc. But if single ended one is required I think it really is feasible (since I did that) with really careful layout.
a) have the bandwidth and input freq ration > 10 (try 20 or 30) - the 10 is used during calculations to neglect part of the equation. 10 in this case means >> so you kill part of your equation what allows you to simplify it enough for hand calculations.

b) try to run VCO on more that 10MHz. Use post divide to slow it down.
Do not use min L.

c) good luck

 

[xwcwc1234]

To Teddy,
Thanks for your advice. I noticed that in some papers the bandwidth/input freq. far more that 10 , for example, around 300. So what is the optimum ratio of bandwidth/input freq. for PLL design ? How to calculate the overall PLL noise ?

 

[Teddy]

10x and more
how to calculate? - I use a little prayer.
The best bet would be to use already proven VCO and filter - if possible.
The problem with the VCO frequency of 300 is that you would have to divide down a lot - another source of jitter. I have seen a dramatic increase of jitter when output divide was more than 8