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To survive under this high 100MV stress,
the protection device (no matter diode/mosfet) must turn ON as mamy as possible during ESD stress. You probably need some triger ckt to help all protection device turn ON as fast & as mamy as possible. There are some ESD papers talking about this issue, you may find them on the forum.
The usual trick for dealing with a shunt capacitance is to adjust a series inductance so that a low pass filter is formed with flat response. This does not always work since the filter may cut off your signal.
1.IEEE Journal of Solid-State circuits June 2002 pp760
"A 0.8-dB NF ESD-Protected 9-mW CMOS LNA Operating at 1.23GHz"
2.IEEE Journal of Solid-State circuits Aug. 2000 pp1194
"ESD Protection Design on Analog Pin with very Low Input Capacitance for High-frequency or Current-Mode Application"
- This paper shows 1pF input capacitance which should be good enough for 100MHz operation.