I wanted to implement 1 HZ square wave in verilog with out giving system clock signal as input.in which first 500 ms the signal should be high,and remaining 500 ms the clock should be low. i write the delay program by using my logic but clock is always high
anyone please help me .what is the error in this program.or give me logic how to create synthesizable delay of 500 ms .I browsed a lot regarding delay, while doing so I came across a delay formula # num).but it is only for simulation.when approaching to synthesizing this delay formula does not work.
The shown logic won't even work with an input clock. It's missing an edge sensitive condition in the always block, required to make a clock counter.
Your stumbling upon the fundamentals of programmable logic design. I presume there are some examples or tutorial designs shipped with the PSoC development tools?
It is for actual hardware. Iam using psoc 3. 1000 ms corresponds to 1 HZ. so iam using counter that counts up to 1000. In it there was a high pulse upto 500 and remaining 500 as low pulse. i don't know this method is correct or not. for simulation we use delay such as( #num).
for example # 5 a=b .but for synthesis it is not possible. my ultimate aim is to produce 500 ms delay .in that delay signal should be high. and also produce another 500 ms delay in this delay signal should be low. i need 1 HZ pulse using this delay.should not use clock as input signal....
This means your counter needs to count up every ms. Which equals an counter clock frequency of 1kHz.
Where do you think this frequency does come from? --> it needs an input clock.
This means your counter needs to count up every ms. Which equals an counter clock frequency of 1kHz.
Where do you think this frequency does come from? --> it needs an input clock.
is there any option to produce 500 ms delay without using counter in verilog. because counter needs clock input. Iam unable to use clock as input signal.
is there any option to produce 500 ms delay without using counter in verilog. because counter needs clock input. Iam unable to use clock as input signal.
Square up a suitable RC output?
You mentioned a PSOC 3 - it always has a clock of some sort otherwise it would not run.
However one important consideration is how accurate the 1Hz needs to be and over what period of time (drift) and this has not been mentioned at all.
Susan