1.5/3/6 MHz Clocks from 50 Mhz On-board Clock using PLL ...

[SyedSJ]

Hello friends

In my project 'FPGA Implementation of OFDM PHY - 802.11a Complaint', I hav to support 3 mandatory data rates of 6/12/24 Mbps.

The Frequency on which the PHY-MAC interfacing module (PLCP) is running is computed to be 1.5/3/6 MHz for 6/12/24 Mbps respectively. The rest of my design is running at 18 MHz and am acheiving the target of 4µs/symbol during simulation.

Now, to take my project to the FPGA kit (DE-2), i hav to synthesize the 3 above mentioned clocks from the on-board clock of 50 MHz. However, the PLL IP core provided by the Altetra (for cyclone II), is un-able to synthesize the 1.5/3/6 MHz clocks from 50 MHz clock.

Is their anyway around for acheiving the clocks ?

Thank u and waiting for a response

Regards
Syed Shaheer Javaid

 

[firefoxPL]

check out this topic

 

[SyedSJ]

Re: 1.5/3/6 MHz Clocks from 50 Mhz On-board Clock using PLL

Thanks for ur reply

But .exe is not opening .... THE APPLICATION FAILED TO INITIALIZE PROPERLY is the message ...

Can u help me in that ?

 

[firefoxPL]

you don't have Microsoft .NET installed

 

[SyedSJ]

Re: 1.5/3/6 MHz Clocks from 50 Mhz On-board Clock using PLL

ok Thanks ... im installing it now to see ur work ...

 

[firefoxPL]

I just realized that my soft will not calculate values for 1.5MHz since it is designed to have only integers as input values, later I will change it and upload a new version, for now you can put 100MHz as input and 3MHz as output, it should be the same as for 50/1.5

Added after 4 minutes:

when you'll manage to run it, I suggest you increase width parameter to get more precise output clocks

 

[j_andr]

Re: 1.5/3/6 MHz Clocks from 50 Mhz On-board Clock using PLL

/.../ the PLL IP core provided by the Altetra is un-able/.../

simpler, what does not mean better, solutions then sugested by firefox
could be - generate by pll 24MHz out of the input 40MHz and then divide
it by 4, by 8 and by 16 using a simple counter

 

[firefoxPL]

yes it's simpler but from my experience using phase accumulator is more reliable and it really doesn't take much resources

 

[SyedSJ]

Re: 1.5/3/6 MHz Clocks from 50 Mhz On-board Clock using PLL

Thank u all for such vibrant support ...

 

[firefoxPL]

Re: 1.5/3/6 MHz Clocks from 50 Mhz On-board Clock using PLL

I just realized that my soft will not calculate values for 1.5MHz since it is designed to have only integers as input values, later I will change it and upload a new version, for now you can put 100MHz as input and 3MHz as output, it should be the same as for 50/1.5

It looks that I was wrong, it will accept real values, just .NET takes into account regional system settings therefore in some countries one must enter 1.5 and in others 1,5 it just depends on the OS language

I just didn't remember the code of the software and since I always write 1.5 it didn't work but when I've put 1,5 it works nicely

 

[mami_hacky]

well, i think that firefoxPL has solved your problem, any how, using a sparatan 3 device, your desired clock frequencies are easily achievable using the CLKDV and CLKFX outputs of DCM

if the problem is still remaining tell me and i'll tell u how to set the parameters

 

[echo47]

mami_hacky, DCM would be a good answer for Xilinx FPGA, but the question is about _Altera Cyclone II.

 

[firefoxPL]

and some if not most DCM's can't produce frequency lower than f.e. 12MHz