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Using only an FPGA? Which type? How much jitter does the 50 MHz clock have, and how much jitter can you tolerate at 1.024 MHz? Your options vary depending on those factors.
Some FPGAs have DLL or PLL clock synthesizers for generating clock frequency ratios. Your ratio is 64/3125, so you would probably need to cascade two synthesizers, plus a counter. For example, multiply by 8/5, then by 8/5, then divide by 125.
If your application can tolerate 20ns of jitter, you could build a simple ratio counter that outputs 64 pulses for every 3125 input pulses.
For lowest jitter, use an external PLL synthesizer chip.
I want to tell you one thing that i can get a clock frequency of 1.0204Mhz where i divided the 50Mhz clk with 49. 50/1.024 comes around 48.86... so i rounded of to 49 and got that 1.0204Mhz clk. As i am going to use this clk for PCM data transfer will this 1.0204 clk will make any effect or this clk is sufficient.
Can we divide 50 by exact 48.86?. Up to my knowledge its not possible i guess.
If any one can come up with the answer it wud be helpfull