1.024 Mhz Clock Generation

[sudhirkv]

50 mhz pll clock divider

HI,


How to generate a Clock frequency of 1.024 MHZ from a 50 MHZ clock.

 

[master_picengineer]

clock oscillator 1.024mhz

Hi,
You have to use a PLL to do this.

 

[echo47]

lattice fpga pll clock ratio

Using only an FPGA? Which type? How much jitter does the 50 MHz clock have, and how much jitter can you tolerate at 1.024 MHz? Your options vary depending on those factors.

Some FPGAs have DLL or PLL clock synthesizers for generating clock frequency ratios. Your ratio is 64/3125, so you would probably need to cascade two synthesizers, plus a counter. For example, multiply by 8/5, then by 8/5, then divide by 125.

If your application can tolerate 20ns of jitter, you could build a simple ratio counter that outputs 64 pulses for every 3125 input pulses.

For lowest jitter, use an external PLL synthesizer chip.

 

[sudhirkv]

1.024 mhz

Am going to implement it in a FPGA and the design is not so fast so ican manage the jitter. is it possible without using PLL or DLL.


Thanks

Sudhir

 

[telga]

Hi,

You can show this topic :

Telga

 

[sudhirkv]

I want to tell you one thing that i can get a clock frequency of 1.0204Mhz where i divided the 50Mhz clk with 49. 50/1.024 comes around 48.86... so i rounded of to 49 and got that 1.0204Mhz clk. As i am going to use this clk for PCM data transfer will this 1.0204 clk will make any effect or this clk is sufficient.

Can we divide 50 by exact 48.86?. Up to my knowledge its not possible i guess.

If any one can come up with the answer it wud be helpfull

 

[viveklengade]

can you give some more details like which FPGA u r using whether it supports to the DCM... to generate fractional clock

 

[sudhirkv]

Hi Vivek

Am using Lattice Semiconductor FPGA (Lattice XP 6C 256Pin ).

 

[echo47]

1.0204 MHz does not equal 1.024 MHz. Are you sure the error would be acceptable?

The LFXP6 data sheet says it contains two sysCLOCK PLL frequency synthesizer blocks. How about using them as I suggested earlier?

I don't know what you mean by "manage the jitter", but if your system really can tolerate 20ns of clock jitter, then use a simple 64/3125 ratio counter.

 

[sudhirkv]

Hi Echo Thanks for u r comments. But i may have to use the PLL for to generate higher frequency.

If its not possible with with clock divider i will go for that.

Thanks all. But still i feel there will be an option to generate 1.024Mhz without using PLL.


Please let me know when u get the answer

Thanks Once again

 

[echo47]

A ratio counter (or ratio divider) is digital. No PLL. But it has lots of jitter. You can't avoid the large jitter unless you use an analog technique such as DLL, PLL, DDS, etc.

Here's a jittery ratio divider. The output reads 1.024000 MHz on my frequency counter with one-second gate:

module top (clk, out);
  input             clk;                             // 50 MHz oscillator
  reg        [12:0] count = 0;
  output reg        out = 0;

  always @ (posedge clk) begin
    count <= count + (count[12] ? 3125-128 : -128);  // ratio = 128/3125
    out <= out + count[12];                          // divide by 2
  end
endmodule