jimmy_tag
Member level 2
its my first basic code which is completely working fine...
Its specially for all those beginners who dont know how to divide (decrease) the clock speed...
u can also check out my video => https://www.youtube.com/watch?v=RrPzS5FLz3k
codes are as follows:
Counter code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity c09 is
port( rst,clk: in std_logic;
op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;
architecture count of c09 is
component clk_div
Port (
clk : in std_logic;
rst : in std_logic;
op : out std_logic
);
end component;
component segd
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end component;
signal flag: std_logic;
signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal c: std_logic_vector(3 downto 0);
signal d: std_logic_vector(3 downto 0);
begin
c1: clk_div port map(clk,rst,flag);
process(rst,flag)
variable m0: std_logic_vector(3 downto 0):="0000";
variable m1: std_logic_vector(3 downto 0):="0000";
variable m2: std_logic_vector(3 downto 0):="0000";
variable m3: std_logic_vector(3 downto 0):="0000";
begin
if rst='0' then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= "1001" then
m0:= m0 + 1;
elsif m0="1001" and m1 /= "1001" then
m0:="0000";
m1:= m1 + 1;
elsif m1="1001" and m2 /= "1001" and m0="1001" then
m1:="0000";
m0:="0000";
m2:= m2 + 1;
elsif m2="1001" and m3/= "1001" and m0="1001" and m1="1001" then
m1:="0000";
m0:="0000";
m2 :="0000";
m3 := m3 + 1;
elsif m3="1001" then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
end if;
end if;
end process;
z0: segd port map(a,op0);
z1: segd port map(b,op1);
z2: segd port map(c,op2);
z3: segd port map(d,op3);
end count;
seven seg lookup table code:
library ieee;
use ieee.std_logic_1164.all;
entity segd is
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end segd;
architecture sseg of segd is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;
most imortant CLOCK CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity clk_div is
Port (
Clk : in std_logic;
rst: in std_logic;
op : out std_logic
);
end clk_div;
architecture RTL of clk_div is
constant max_count : natural := 6000000;
begin
compteur : process(Clk,rst)
variable count : natural range 0 to max_count;
begin
if rst = '0' then
count := 0;
op <= '1';
elsif rising_edge(Clk) then
if count < max_count/2 then
op <='1';
count := count + 1;
elsif count < max_count then
op <='0';
count := count + 1;
else
count := 0;
op <='1';
end if;
end if;
end process compteur;
end RTL;
If you get any quries about my code... then do comment..
Suggetions are also accepted...[/b]
Its specially for all those beginners who dont know how to divide (decrease) the clock speed...
u can also check out my video => https://www.youtube.com/watch?v=RrPzS5FLz3k
codes are as follows:
Counter code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity c09 is
port( rst,clk: in std_logic;
op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;
architecture count of c09 is
component clk_div
Port (
clk : in std_logic;
rst : in std_logic;
op : out std_logic
);
end component;
component segd
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end component;
signal flag: std_logic;
signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal c: std_logic_vector(3 downto 0);
signal d: std_logic_vector(3 downto 0);
begin
c1: clk_div port map(clk,rst,flag);
process(rst,flag)
variable m0: std_logic_vector(3 downto 0):="0000";
variable m1: std_logic_vector(3 downto 0):="0000";
variable m2: std_logic_vector(3 downto 0):="0000";
variable m3: std_logic_vector(3 downto 0):="0000";
begin
if rst='0' then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= "1001" then
m0:= m0 + 1;
elsif m0="1001" and m1 /= "1001" then
m0:="0000";
m1:= m1 + 1;
elsif m1="1001" and m2 /= "1001" and m0="1001" then
m1:="0000";
m0:="0000";
m2:= m2 + 1;
elsif m2="1001" and m3/= "1001" and m0="1001" and m1="1001" then
m1:="0000";
m0:="0000";
m2 :="0000";
m3 := m3 + 1;
elsif m3="1001" then
m0:="0000";
m1:="0000";
m2:="0000";
m3:="0000";
end if;
end if;
end process;
z0: segd port map(a,op0);
z1: segd port map(b,op1);
z2: segd port map(c,op2);
z3: segd port map(d,op3);
end count;
seven seg lookup table code:
library ieee;
use ieee.std_logic_1164.all;
entity segd is
port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end segd;
architecture sseg of segd is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;
most imortant CLOCK CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity clk_div is
Port (
Clk : in std_logic;
rst: in std_logic;
op : out std_logic
);
end clk_div;
architecture RTL of clk_div is
constant max_count : natural := 6000000;
begin
compteur : process(Clk,rst)
variable count : natural range 0 to max_count;
begin
if rst = '0' then
count := 0;
op <= '1';
elsif rising_edge(Clk) then
if count < max_count/2 then
op <='1';
count := count + 1;
elsif count < max_count then
op <='0';
count := count + 1;
else
count := 0;
op <='1';
end if;
end if;
end process compteur;
end RTL;
If you get any quries about my code... then do comment..
Suggetions are also accepted...[/b]