0.35um 3.3V NMOS transistor with gate applied to 5.0V, it is ok?

[samuel]

hello ,everyone

Now ,I want a moscap with inversion mode. can i apply 5V to 0.35um_3.3V_NMOS gate?

if not, why?

 

[kemiyun]

Hello,

Tricky answer, of course you can. Actually you can even apply 10000 billion volts to the gate. However its source and bulk should be 10000 billion - 3.3V at lowest point in this case. It doesn't matter what voltage you apply to the gate, just make sure that Gate-Source, Gate-Bulk, Gate-Drain voltages are in safe operating area. Otherwise you might burn some gates, which is generally non-recoverable. So as a result:
-Read the PDK documents, see what are the voltage rates of these devices.
-Make sure that transistors stay in these ranges during operation.

By the way if this process is AMS0.35 they do have extensive safe operating area check tools. If it gives any error, you are probably doing it wrong. And one last addition, I don't know which process is this but I don't think they can withstand 5V gate and grounded source-drain-bulk. You might think that there is an inversion layer in between, therefore it shouldn't matter what you put on gate, but think again, there are also overlapping regions between source and drain, so follow the PDK documents to the end

 

[samuel]

thanks, kemiyun

in this case,
first i want a larger moscap in my 5V circuit, so i want replace the thick NMOS（5.0V）capacitor with thin NMOS（3.3V）capacitor；
second , i find the Vbd(breakdown voltage) is 6.5V, so i think that.
third, in my application , nmoscap Vgs(max)=5.0V,Vgd(max)=5.0V,Vgb=5.0(max)

can i do that?

 

[kemiyun]

If those are absolute maximum values, no you can't do that. But look for an explicit statement about maximum terminal voltages. Breakdown voltage is kind of vague definition, breakdown of what? But if it is what you say it is, and these are not absolute maximum ratings, I believe you can do that. But if those can endure 5 V, why are they calling it 3.3V transistors, therefore I suggest you to double check those. Also if you are doing this to get rid of extra well layers for high voltage, think again, because you probably want to isolate these no matter what transistor you use.

I'm sorry for the vague answer, maybe someone with more experience can help you better.

 

[erikl]

... first i want a larger moscap in my 5V circuit, so i want replace the thick NMOS（5.0V）capacitor with thin NMOS（3.3V）capacitor；
second , i find the Vbd(breakdown voltage) is 6.5V, so i think that.
third, in my application , nmoscap Vgs(max)=5.0V,Vgd(max)=5.0V,Vgb=5.0(max)

can i do that?

ERC run would give you error messages. Perhaps you could get a waiver from the fab, by this loosing any guarantee (for sure they'd prefer to sell you a larger chip, which you'd probably need if you go with 5V NMOS).

And if it works ok for the first lot, it doesn't mean it would work for the following ones. Is it really worth to take such a risk?

 

[dick_freebird]

It is quite possibly survivable. Your transistor "voltage"
is the least of all passing reliability stress conditions,
often this is D-S and derived from hot carrier reliability
with G-S, G-D higher by maybe a volt and BVox I'd
guess in the 8V range short term.

It's easy to electrically determine whether any gross
damage has occurred.

But if you're looking for somebody to guarantee you
that you didn't hurt it at all, consider yourself screwed.
Nobody has any incentive to take your responsibility
for abuse and subsequent failure and make it theirs.
So the foundry will give you no paper. Doesn't stop
customers from trying, and going as far as trying to
threaten the vendor. But it's real easy to turn that
around with a word to their management about silly
reliability-threatening junior engineer foolery.

You will not get any responsible foundry to bless a
violation of its device application rules. What you
think and what you think you can prove, will not
make the mountain come to you.