maximum voltage for 0.18um
OK, let's keep in touch. Im working with TSMC 0.18 1P6M mixed signal process. Here is where I am now:
- I'm trying to avoid any lab testing to save time. But if you get lab measurements, you can get an estimate of degradation under DC stress conditions. However, if your circuit works under AC (switching transistors or analog blocks etc.), the lifetime can be much longer because the real HCI degradation only occurs when the devices work in the linear region. To get the AC lifetime estimate, simulations with real circuit need to be run.
- The papers say that the HCI degradation is a function of the substrate leakage current for NMOS and gate leakage current for PMOS. Regular spectre simulations with current TSMC models give quite inaccurate estimate for substrate leakage and does not simulate gate leakage at all.
- I found that Spectre HCI degradation analysis only works with BSIM level 2, so it's useless
- The real solution is a tool called RelXpert offered by Cadence - this is a degradation simulator that requires additional model parameters for simulating leakage currents, aging etc. Those model parameters can be either extracted in the lab (by usinng Cadence BsimProPlus model extraction tool), or acquired from somewhere else. Right now I'm trying to find out if I can get those RelXpert models from TSMC or Cadence.
I'll email you some info later.