Closed loop question and time response

Hi everyone,

I would like to know if this statement/question makes sense: the closed loop is taking too long to react. Can someone tell me what this exactly means?

Another question, how is the closed loop related to the settling time?

Regards

Without further information, "closed loop" is irrelevant. You are analyzing the frequency and time domain transfer functions of a linear system. They are directly related by Fourier respectively Laplace transformation, but the analysis is the same if the system is designed as a closed loop feedback system or open loop system without feedback, e.g. a passive filter.

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Excessive setting time can be either caused by an oscillating step response (frequency domain transfer function has poles with high Q) or a "creeping" long tail (gain drop far below the cut-off frequency).

The dynamic of a system is determined by its closed loop poles( in case feedback is applied) or simply poles of the transfer function i.e. the zeros of its characteristic polynom.
Once you know where are your poles, you know how the system will react i.e. its dynamic.

Thanks for your reply guys.

What else can I say. What I mean is, if you want to check the stability you could put a vdc voltage source at the input, at the output step the current from 0uA to something else and see how the circuit behaves. What I am noticing is that for one design I get a very big dip, the circuit recovers and remain stable. The second on it has a dip, but much lower that the first one. The differences I would say is the sizing of the current mirror load in the diff. pair and consequently the CS in the second stage.

I am trying to figure out what might happening. I think it could be something related to the closed loop taking too long to react? In one case is reacting slowly, that is, it has some delay, that's why when I do a step at the output, current step, I get a bigger dip.

Regards.

You are apparently referring to a specific circuit and transient response case (load step of a voltage regulator). It would be reasonable to discuss the problems related to a circuit schematic or block diagram.

The mentioned details raise the question if the observed behavior might be caused by non-linear effects which are beyond a linear system description in frequency and time domain.

Hi again. It's not a regulator it's a 2 stage amplifier (thr basic 2 stage amplifier) and I am trying to perform a current step at the output, taking into account it is connected in unity gain.

CAMALEAO said:

Hi again. It's not a regulator it's a 2 stage amplifier (thr basic 2 stage amplifier) and I am trying to perform a current step at the output, taking into account it is connected in unity gain.

Click to expand...

If the step response is slow, it means that Closed Loop Bandwidth is too narrow.

Yeah, I understand your point. But accordingly to this expression: BW = 0.35/tr, which relates the BW with the rise time of the voltage applies, I have enough BW. My BW in unity gain is around 500kHz and using a 1us rise time the BW is around 350kHz.

So I should be able to have a stable and nice response right?

The load step response will depend on multiple parameters
- loop bandwidth
- open loop output impedance (respectively close loop output impedance according to OL impedance and loop bandwidth)
- possible non-linear effects

Referring to your calculation, a large close loop bandwidth (= bandwidth of the amplifier with feedback) doesn't necessarily imply a large loop bandwidth.

Are you driving any output capacitance? Any amplifier BW or rise time is determined for a known load capacitance (for instance 10pF, 50pF, 100nF). If the output rise/fall time is 300ns with a 100pF cap (or a parasitic capacitance), it will be much longer with a 1nF one.

Thank you all for your comments.

Klauss, you have mentioned the output impedance and I haven't thought about it. Can I ask you something about this?

I am experiencing the following: when a step the output current, from zero to, say 80% of the bias at the output, the amplifier has a ring but it settles. However, when I step it with 90% of the bias current, the amplifier takes a longer time to settle. In both cases, either with a longer or shorter rise times (1us or 10us), with 90% of output bias current, the settling time still longer when compared to a step with 80% of the bias current at the output stage. It looks like that the transistor at the output goes to cut-off because I am taking away current from the biasing.

Now I wonder, if I want to see the stability of the amplifier, I can use the body plot. Nevertheless, if I want to use transient as well, what are the best ways to test the amplifier or take the amplifier to its limits?

I was thinking: dc voltage at the input and current step at the output as well as a current squarewave at the output with something around 80% of bias current.
Then the other way around. Squarewave voltage at the input and do the same at the output as mentioned above. All of this in unity gain mode.

Now, does this make any sense? How could I test an amplifier using transient?

Regards

CAMALEAO said:

I was thinking: dc voltage at the input and current step at the output as well as a current squarewave at the output with something around 80% of bias current.
Then the other way around. Squarewave voltage at the input and do the same at the output as mentioned above. All of this in unity gain mode.

Now, does this make any sense? How could I test an amplifier using transient?

Click to expand...

In my opinion, testing your amplifier against square wave is useless because the square wave is just step inputs applied to it (step after step after step..). What I am trying to say is that you only have to worry about a step input and design accordingly. If you are satisfied with the transient response to the step, you will be satisfied to transient response on square wave input.

I understand your point of view. I just was asking that because, although it is a series of steps (the squarewave), you are forcing the amplifier to go from zero to X% of bias current and right after down, from X% to zero. It is like if you were forcing two states one after the other which might give you another result when compared to on a step from 0 to X%. But I see your point. Thanks for the comment.