PIC18F - Updating CCPR1 avoiding unexpected interrupt

pic18f + interrupt not generated

Micro family 18F

Module CCP1 in compare mode against TMR1 in timer mode.

Setting: "toggle output pin (RC2) on match" condition.

My application currently loads alternatively CCPR1H:L with HALF_T1 and HALF_T2 and restarts TMR1. (It works OK like that).

Trying to follow the frequent advice received, to leave TMR1 running alone and ADDING the next value to CCPR1H:L, here is my question:

How to add the low and high bytes of next HALF_Tx, without risking to have an undesired match BEFORE both are added? In extreme cases this actually WOULD happen in my application. Tested.

For other settings I know how to do it (changing CCP1M0) but no for "toggle on match". Any change of a single bit from CCP1M3:CCP1M0 would enter in an undesired condition, so I discarded that.

I find this problem mentioned somewhere but no solution explained for this case.

I want to retain the "toggle on match setting".:!:

Help appreciated.

Hi, If you get a match and toggle RC you can also generate an interrupt at the same time and change the value in the interrupt routine. This works since timer will be cleared to on a match condition, and your code is fast enough to update or change the compare value before it reaches a new value. Best is to update the new CCPR1, follow the write order explained in the datasheet, believe its first low part followed by high part. regards, Paul.

Hola Paul,

There is no reccomended order to update CCP registers. That's why my question.

It is TMR1 which has a reccomended sequence which doesn't apply here.

Hi, It does not matter if you update it in a interrupt routine just after the timer did get a reset !. I do the same and it works perfect, first I update low part followed by high part.

Paul.

Updating in that way, depending of the values, could make that we get a match before I have time to update the high part. That's exactly what I want to avoid.

Manual doesn't recommend any special sequence. I wish it was possible!

Hi, I think you do not understand what I mean !. You only need 2us after the interrupt to update the compare register !. The interrupt is generated by the compare itself !. You should not start updating CCPR1 just like that !.