rakesh_aadhimoolam
Full Member level 4
hello folks.........
the use of package in VHDL cannot be used in Verilog...
so does anyone have idea or code of a simple ROM design........in VERILOG
thanks
the use of package in VHDL cannot be used in Verilog...
so does anyone have idea or code of a simple ROM design........in VERILOG
thanks