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standard cell library achitecture

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Hi,
Recently I encounter the following problem when I want to design a standard libray under submicron SOI technology.
as follow
1 How to ascertain unit drive strenth ,such as INVX1?
2 How to acquire the P/N width ratio of INVX1?Addtionally,What's the difference between the ratio of CLK buffer and that of Ordinary buffer?
3 In order to characterization a library ,how to stucture a set of operating point involving input skew and output load?

Thanks a lot!
 

1. X1 is when minimum length/minimum width nmos transistors are used in the gates?
2. The difference between CLKBUF and BUF is that CLKBUF is designed with a lot more care payed to matching rise/fall delays through the cell.
3. You pick a maximum load used in your design and maximum allowed slew. Then evenly space out N (mostly 4-6) characterization points between 0load/slew and max load/slew.
 

Thanks!
1 X1 should be the minimum driven strength in the library,except the mininmum input capacitance cell which need to consider low power XL.

2 I wonder ordinary BUF how to ascertain the P/N width ratio,please show me your view,thank you

3 Similary,I wonder how to get the N points?addtionly please.
 

hi, eternal_nan, perhaps evenly space out N (mostly 4-6) characterization points between 0load/slew and max load/slew is not correct.
 

Perhaps it is not, that was my understanding but standard cell characterization is slightly outside of my area of expertise.

Can you elaborate a bit on the correct answer?
 

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