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who knows how to reduce the EMI at IC design level , especially in digital design,and not at board level ? how to reduce EMI in circuit design?
thanks.
who knows how to reduce the EMI at IC design level , especially in digital design,and not at board level ? how to reduce EMI in circuit design?
thanks.
who knows how to reduce the EMI at IC design level , especially in digital design,and not at board level ? how to reduce EMI in circuit design?
thanks.
It's not the best thing sometimes. By doing that in an IC, you will increase the capacitance to GND related to all the nodes..that means bigger delays and maybe need for bigger/more powerful digital cells
Hutaoreal...can you be more explicit about what kind of circuit you have in mind?
What I know is we usually reduce EMI on board. Maybe it is the main solution we have. Also we have some technic on layout design to reduce it and SSCG is a normal way in high speed design. But I want to know some technics on logic design that also can works on it except what I mention above.
I conclude SSCG in analog circuit, but what is the solution in digital circuit design?
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