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[SOLVED] Find the active load effect of differential op amplifier

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jiangwp

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When a op amplifier is designed, some problems are appeared.

For a differential op,

1.the input differential pair determines the input transcondutance ,input

common mode range and referred input noise;

2.the common bias current source determines the input transcondutance , slew

rate ,input common mode range and CMRR;

But for the active load, i know only the gain is related it.

in fact, the gain is related load transistor length (L), what determined active load tansistor width?

Maybe , the active load does effect in the IMR or output swing.

what else effects about the active load transistors and how to designed its size?
 

jiangwp said:
When a op amplifier is designed, some problems are appeared.
in fact, the gain is related load transistor length (L), what determined active load tansistor width?
quote]

U increase the length of the active load transistor to increase its output resistance, to acheive high gain.

At the same time, when the length is increased, the width of the transistor should be increased with the same ratio so as not to affect the current passing through the branch to which it is connected.
Click to expand...
 

Based on MOS working situation, doing device simulation to get the suitable lenth maybe a effective method.
 

There are other ways to calculate W/L for active loads. Usually designers choose Vdd/2 as Vocm and for a desired symmetric output swing you can calculate the voltage headroom over these active loads. as a rule of thumb we often choose veff of each active device (if we use two stacked MOS trs as the active load)
Veff = (Vdd/2 - outswing/2)/2.
By having µCox of the device and its current (from bandwidth or slew rate) we can calculate W/L of active load devices:
I = 1/2*µCox*(W/L)(Veff)^2

Regards,
EZT
 

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