ANALA
Member level 1
Greetings,
I have simulated a CMOS inverter in LTspice using the following specifications
Supply voltage 0.2V
NMOS & PMOS Length(L)=32n
NMOS Width(W) =32n
PMOS Width(W) =64n
NMOS Drain/Source Area=2f
PMOS Drain/Source Area=4f
NMOS Drain/Source Perimeter=192n
PMOS Drain/Source Perimeter=256n
Threshold Voltage(Vth0) NMOS=0.3558
Threshold Voltage(Vth0) PMOS=-0.24123
...How do i perform the best case and worst case delay analysis?
I have simulated a CMOS inverter in LTspice using the following specifications
Supply voltage 0.2V
NMOS & PMOS Length(L)=32n
NMOS Width(W) =32n
PMOS Width(W) =64n
NMOS Drain/Source Area=2f
PMOS Drain/Source Area=4f
NMOS Drain/Source Perimeter=192n
PMOS Drain/Source Perimeter=256n
Threshold Voltage(Vth0) NMOS=0.3558
Threshold Voltage(Vth0) PMOS=-0.24123
...How do i perform the best case and worst case delay analysis?