Guardring placement for analog circuit layout design

There are 10 pmos transistors with identical size, for example, 10um/5um . I would like to do the analog circuit layout, and match them well.

As shown in the figure, the red line is the n-guardring, which is connected to nwell; the blue line is the p-guradring, wihch is short to ground.

In Fig.1, each transistor is cycled by its own n and p guradring. The neiboring nwell should have a certain space requirement to meet the drc rule, so each block has to be placed far away, which is not space efficient.

In Fig.2, the total 10 transistors are shared only one n and p guardring.

Questions:
1. For Fig.2, is there a latchup issue since not every transistor has been cycled by the n and p guardring?
2. Which one is a good design?

Thanks.

shanmei said:

There are 10 pmos transistors with identical size ...
1. For Fig.2, is there a latchup issue since not every transistor has been cycled by the n and p guardring?

Click to expand...

No latchup possible: if there aren't any near nmos transistors close to (or within) the n-well. DRC will tell you.

shanmei said:

2. Which one is a good design?

Click to expand...

Fig. 2

shanmei said:

As shown in the figure, the red line is the n-guardring, which is connected to nwell; the blue line is the p-guardring, wihch is short to ground.

Click to expand...

If the red ring is inside the n-well (n+ on n), you should call it a body tap ring.
If it is outside the n-well, you better reverse the red and the blue ring: the p-guardring (p+ on p) next to the n-well (DRC will tell you the min. spacing), and the n+ on n-guardring (if any, usually not necessary) around the p-guardring (DRC min-spacing, again).

Your above given connections are correct.