LearningSoMuch
Newbie level 2
How would I replicate this VHDL process into Verilog
I am kind of new to this so I was just confused on this part. If someone could please show me how this process in Verilog would look, that would be helpful.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 adding : process(a, b, inaddress, out) is variable addm :unsigned(32 downto 0); begin addm := ('0' & a) + ('0' & b) + inaddress; out <= addm(31 downto 0); inout_t <= addm(32); backout <= (addm(31) and not a(31) and not b(31)) or (not out(31) and a(31) and b(31)); end process;
I am kind of new to this so I was just confused on this part. If someone could please show me how this process in Verilog would look, that would be helpful.
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