hareesh007
Newbie level 1
I am newbie in FPGAs. I work on Xilinx FPGAs and on Xilinx ISE 14.7 IDE (Yet to learn Vivado). I would like to know about the scope of STA in FPGAs. Whenever I design something in FPGAs and fail to meet timing in FPGAs, what I do is playing around in HDL codes and set design goals to "best timing performance" in Xilinx ISE. Nothing more than that. Somehow I meet timing using them. But I dont feel I am good, if some body asks me if I am good in Timing Verification. Because I learnt so much in STA theory during by graduation, but not applying much in my FPGA designs. I don't know if we can do more in FPGAs regarding timing, other than coding tweaks and using ISE tool specific options. I feel ASICs have more flexibility than FPGAs in this aspect. What more we can do about STA in Xilinx ISE, if timing fails ? Can we manually do placing and routing ? But I think tools are programmed to do the best possible routing. So we can't do much about it ? I hope somebody puts some light on this post.