anilineda
Member level 3
How can i write testbench and monitor all the AXI4 bus signals in vivado ??
I created a simple block design in vivado . it is just a axi4 system having a microblaze, a DDR3 module and a UART-lite. i generated a bit file for this and programmed on vc707 and verified "hello world" program in SDK and mwr and mrd instructions in xsdb console.
my question is , how can i write a testbench and simulate it , so that i can see all axi4 bus signals i.e i want to indirectly figure out the axi4 protocol from those wave forms. please don't say about BFM, i don't have a licence for that.
i am very new to this, if possible provide me the testbench.
I created a simple block design in vivado . it is just a axi4 system having a microblaze, a DDR3 module and a UART-lite. i generated a bit file for this and programmed on vc707 and verified "hello world" program in SDK and mwr and mrd instructions in xsdb console.
my question is , how can i write a testbench and simulate it , so that i can see all axi4 bus signals i.e i want to indirectly figure out the axi4 protocol from those wave forms. please don't say about BFM, i don't have a licence for that.
i am very new to this, if possible provide me the testbench.