understanding verilog code

Hi, im new to verilog. im trying to understand a code provided by xilink to create a multiplexer. the code is as follows:


the ".I0" part, what kind of operator is that? didnt find any reference to "dot" operator.

don't know what you mean. .IO(data_in[0]) is standard Verilog module instantiation syntax. The dot is required for the port identifier in named port connection, review your Verilog text book or language reference.

I don't think you should use such code if you want to learn verilog (or VHDL).
You should learn to write more general code. The Xilinx mux code will not work for ASIC design. I don't know if it will work on any other FPGA than Xilinx.

You should describe the mux with a "case" statement, that will work in any technology:
https://www.asic-world.com/examples/verilog/mux.html

std_match said:

I don't think you should use such code if you want to learn verilog (or VHDL).

Click to expand...

Agreed, don't use device specific primitives to construct structural code. Synthesis tools are designed to do that.

The Xilinx mux code will not work for ASIC design. I don't know if it will work on any other FPGA than Xilinx.

Click to expand...

It won't work for xilinx parts that don't have LUT6 primitives.

Hi all,

thank you for all the reply. what im trying to do is making a fast multiplexer, and xilink has SLICEL that is dedicated for fast multiplexer, and the code above is past of the code provided by xilink, and the LUT6 is part of it. but i cannot understand the code as i have not seen anything like that. been trying to google it, look in some book in operator section, didnt find it. hope this clear about my problem.

so FvM said that it is a port identifier, in a named port connection. does that mean it was an identifier for a specific port in xilink's FPGA? that there is a specific port in the hardware that is under LUT6 module with .I0 to .I5 port?

Hello,

As suggested in previous posts, you should refer to some verilog textbook. you need to understand how a verilog module is instantiated and its ports are connected to other modules/signals. Any basic verilog tutorial should give you clarity to understand what is formal and actual port name in module instance. i.e. in your case LUT6 is a module, a kind of template used for creating specific instance where port I0 is connected to data_in[0] port.

A vendor synthesis tool can be expected to implement frequently used HDL constructs like multiplexers in an optimal way, so designing with low level primitives shouldn't be required regularly. Low level primitives have a purpose in handling specific design problems beyond the scope of mainstream FPGA applications, or avoiding known weaknesses of a design tool.

does that mean it was an identifier for a specific port in xilink's FPGA? that there is a specific port in the hardware that is under LUT6 module with .I0 to .I5 port?

Click to expand...

According to Verilog syntax, the ports are named I0 to I5, not .I0 to .I5. The LUT6 primitive is e.g. described in the "Spartan-6 Libraries Guide for HDL Designs". Curiously you are stumbling upon trivial syntax, but the involved part of the code is the meaning of the 64-bit INIT word...

exceeder88 said:

xilink has SLICEL that is dedicated for fast multiplexer, and the code above is past of the code provided by xilink, and the LUT6 is part of it. but i cannot understand the code as i have not seen anything like that. been trying to google it, look in some book in operator section, didnt find it. hope this clear about my problem.

Click to expand...

A SLICEL is not dedicated for fast multiplexing. A SLICEL is a logic only slice, similarly a SLICEM is a slice that is also capable of being used as a distributed memory besides being used as logic.

Designing with SLICE logic and/or LUT primitives is a poor way to design something as it's the lowest level you can design FPGA logic circuits. Of course you are having issues with understanding the code as this is similar to designing a counter with discrete gates.

I would suggest not using autogenerated netliststs to learn how to design circuits using an FPGA. Learn VHDL/Verilog and how to run synthesis to produce that netlist. This will be much more practical and will allow you to actually be productive.