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PLL or simple clock divider ?

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Binome

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Hi,
Im using a Cyclone IV FPGA on a DE0-nano board. The original clock is 50MHz and I have to use a 5MHz one. Should I use an included PLL or a simple divider to have a smaller frequency? What are the differences and what is best?
Thanks.
 

Although GCLK networks can be driven by internal logic, e.g. a frequency divider implemented in LEs, I won't do that. Setting up a PLL with 50 MHz input and 5 MHz output frequency is simple and straightforward.

The other option is to use a 50 MHz clock and a 5 MHz clock enable.
 

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