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How to increment a value in verilog?

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keerthna

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I wrote a piece of code for the incrementation of a variable at certain conditions but it is not happening the way it has to be. Can anyone please help me out with the same.

Here is my sample code

Code Verilog - [expand]
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reg[31:0]nomfreq,nc1;
reg [2:0] up,down;
reg high;
initial begin
up=0
down=0;
high=0
end
always@(high)
begin
if(nc1>nomfreq)
up<=up+1;
if(up==2)
begin
newfreq<=nc1;
nomfreq<=newfreq;
end
if((up==1)&&(down==1))
begin
up=0;
down=0
newfreq<=nomfreq;
end


here the up value is not getting increment properly. is there something that i am missing out?
 
Last edited by a moderator:

What variable are you expecting to increment? up?
If so:
Code: 
always@(high)               // there is no information of the level of 'high', which is used to launch current process
begin
if(nc1>nomfreq)
up<=up+1;                   // up send to scheduler to be incremented at the end of simulation cycle
if(up==2)
begin
newfreq<=nc1;
nomfreq<=newfreq;
end
if((up==1)&&(down==1))         // if this condition is true, then assignment 'up=0' will take place immediately
begin
up=0;
down=0
newfreq<=nomfreq;
end

Actually, the code you wrote is a (very) bad coding style example. Think about to rewrite it in some other way.
 

I am incrementing up and down variables. High becomes '1' when a particular value of count is reached like

if(count1==23'b______)
begin
count1=0;
high=1;
end

- - - Updated - - -

I am incrementing up and down variables. High becomes '1' when a particular value of count is reached like

if(count1==23'b______)
begin
count1=0;
high=1;
end
 

Could you post your original code here? It's hard to advice something without it.
For example:
- you shouldn't mix blocking and non-blocking assignment in same process;
- first process you wrote should be 'always@*', not 'always@(high)'.
 

Functional MRI studies have found that subjects writing the above code showed furious activity in the imperative programming part of the brain.

Put another way, you should really try to stick with HDL templates that describe actual hardware. Either from a book or from templates found in IDE's. Or online tutorials. Your current code is a tiny bit softwarey.

Quick links:
https://www.asic-world.com/examples/verilog/up_down_counter.html
https://www.asic-world.com/examples/verilog/up_counter_with_load.html
 

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