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Advanced Member level 4
Hi,
I have the core "EZDMA IP for Xilinx Hard IP" version 1.4.3
I have problems interfacing the PLDA generated core wrapper to Xilinx PCIe Hard Ip.
I want to use xilinx PCIe endpoint block plus version 1.7 but there is some incompatibility!
should I use old versions of xilinx core?
Is there any examples on using ML605 with this PLDA core?
one of important problems is that Xilinx Ip Cores gives a 1 bit input named trn_trem_n but
EZDMA core has a 2 bit output named trn_trem_n(1:0) . how can I connects this ports?
thank for your help.
I have the core "EZDMA IP for Xilinx Hard IP" version 1.4.3
I have problems interfacing the PLDA generated core wrapper to Xilinx PCIe Hard Ip.
I want to use xilinx PCIe endpoint block plus version 1.7 but there is some incompatibility!
should I use old versions of xilinx core?
Is there any examples on using ML605 with this PLDA core?
one of important problems is that Xilinx Ip Cores gives a 1 bit input named trn_trem_n but
EZDMA core has a 2 bit output named trn_trem_n(1:0) . how can I connects this ports?
thank for your help.
