ebuddy
Full Member level 3
I defined a fifo interface:
And my DUT looks like this:
So when I am trying to connect dut in the testbench, I will do this:
Modelsim just complains that "A modport ('dut') should not be used in a hierarchical path"
What is other way to write this and avoid any warnings?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 interface fifoint (); logic clk; logic rstn; logic [3:0] cin; logic [3:0] cout; modport dut (input clk, rstn, cin, output cout); modport tb (input clk, rstn, cout, input cin); endinterface
And my DUT looks like this:
Code Verilog - [expand] 1 2 3 module fifo (input clk, rstn, input [3:0] cin, output reg [3:0] cout); ..... endmodule
So when I am trying to connect dut in the testbench, I will do this:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 module t_fifo (); fifoint mfifoint(); tp i_tp(mfifoint.tb); fifo dut ( .clk (mfifoint.dut.clk), .rstn (mfifoint.dut.rstn), .cin (mfifoint.dut.cin), .cout (mfifoint.dut.cout) ); endmodule
Modelsim just complains that "A modport ('dut') should not be used in a hierarchical path"
What is other way to write this and avoid any warnings?
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