Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
It really depends on the simulation process which currently mainly includes initial simulation including the debugging and testing some basic test cases stage and the regression stage meaning a lot of testing cases are executed when there're rare errors. During the initial stage, which mainly requires the debugging the basic faults during the coding and some easily-found errors of the design, so that this stage will often use some linting stragety and the event-driven simulation methodlogy is utilized with Verilog-XL and VCS with linting options. After that, you'll test the design when there are rare errors will be found and then you can use cycle-driven simulation which means faster simulation performance when you can use NC-verilog of Cadence and VCS with some options.
It depends on Design as well
1) For Asnchronous Design(Networking , comuunications products ) Cadence Tools like NCverilog which is a Event Based Simulator is preferred
2) For SYnchonoua Designs ( Microprocesors ) , Synopsys tools VCS which is a cycle based SImulator is preferred
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
