achaleus
Member level 5
hi all,
I have an designed IP core, which was successfully tested on board(pico M503), now I am doing multiple(same IP) cores
but I am facing timing problems but for single core it is worked fine, I am using smart explorer for various ways of mapping and I am checking there timing scores and slack..
what are the other ways for multiple core instantiation on the fpga to remove timing problems,(I know the reason that while using multiple cores routing problem causes timing errors).. please suggest what are the different ways for efficient utilization of whole FPGA without timing errors ..
thanks,
I have an designed IP core, which was successfully tested on board(pico M503), now I am doing multiple(same IP) cores
but I am facing timing problems but for single core it is worked fine, I am using smart explorer for various ways of mapping and I am checking there timing scores and slack..
what are the other ways for multiple core instantiation on the fpga to remove timing problems,(I know the reason that while using multiple cores routing problem causes timing errors).. please suggest what are the different ways for efficient utilization of whole FPGA without timing errors ..
thanks,