use of multiple IP cores in vertex 6 fpga

[achaleus]

hi all,
I have an designed IP core, which was successfully tested on board(pico M503), now I am doing multiple(same IP) cores
but I am facing timing problems but for single core it is worked fine, I am using smart explorer for various ways of mapping and I am checking there timing scores and slack..

what are the other ways for multiple core instantiation on the fpga to remove timing problems,(I know the reason that while using multiple cores routing problem causes timing errors).. please suggest what are the different ways for efficient utilization of whole FPGA without timing errors ..

thanks,

 

[TrickyDicky]

there is nothing wrong with using multiple IP cores, and theres no technique to improving timing. The problem comes from just too much logic being used, or too many things need to connect to one thing (and stuff has to spread out more).

So for any design that isnt meeting timing, there are several things.
1. The best way to do it is fix the source code - add more pipeling registers and/or reduce the number of layers of logic between registers.
2. Identify and multi cycle paths, and spec them as such.
3. For registers with high fan-out, duplicate the registers and make sure the synthesisor doesnt pack them together again.
4. Use region constraints so that it doesnt place the register too spread out over the chip.
5. as a last resort put max delays on specified paths and apply them to the fitter.