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synchronous data tranfer between two fpga

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reddyanilkumar

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hello any one please help to write a verilog code to for synchronous data transfer between two fpgas..its my finel year project pls any one help.....i am using vertex5 fpga board
 

Hi reddyanilkumar,

You can refer the beow link, its a 7:1 LVDS synchronous transmission, you can configure any one of the FPGA as a Master (Transmitter) and the other one as a Slave (Receiver), you can avoid the video processing parts in the source code, take only the transmitter and the receiver section. Instead of video data you can generates your own data and transmit.

https://www.latticesemi.com/product...eferencedesigns/71lvdsvideointerfaceforec.cfm
 
thanku for replying..i will inform if i have any problem..

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i have designed the transmitter and receiver part in two different fpgas...now i am unable to understand how to transfer the data from one fpga to other...

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and it is serial transfer
 

a couple of questions pop up:
- does the data need to be synchronous in both FPGA's?
- how much data?
- what transfer rate?

and most important one:
- what have you tried so far?
 

If you are using the above design, you can assign 7 bit parallel data port to your parallel data and it will transmit trough the serial port (if it is a transmitter), the serial data coming from the transmitter is decoded and generated the 7 bit parallel data output(if it is a receiver). One another thing is that here 7:1 parallel to serial and 1:7 serial to parallel is happening, like that there are 4 channels are there. You can selects the number of channels as 1, 2, 3 or 4 by simple modification in the code.

One you run the reference design simulation you will understand the concept well.
 

yes data need to be synchronous...
4 bits of parallel data to be sent...
so far we have written code for transmitter and receiver in verilog

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we r unable to understand how to send data..look at this url..and help us
file:///C:/Documents%20and%20Settings/HET-18/Desktop/FPGA%20Serial%C2%A0Communication%20%20%20The%20Green%20Machine.htm
 

if it's only 4 bit of data (I don't know what bit rate you want to achieve), I would just make 4 I/O pins + clk available on both FPGA's, make them both inout (tristate) and you have what you want.

7:1 is then overkill (i know quite well because I worked at Lattice at the time of development of that core) and is intended for use with video.
BTW: the data is delayed for 3 clock cycles - not quite synchronous

Uhm, that link ... can't reach it
 

7:1 means with single channel it will send 7 bits of data with respect to a system clock, like that there are 4 channels. If you are using the 4 channels in a single system clock it will send 28 bits of data (7*4).

One another thing is that for this parallel to serial conversion in the transmitter side and serial to parallel conversion on the receiver side you need a clock which is 3.5 times that of the System Clock., so both the rising and falling edge of that clock(3.5*system_clk) will do the conversions.
 

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