[SOLVED] Layout considerations, Max W to L before having voltage drop over gate

Hello all,

I was wondering from the experienced guys, what the max recommend W to L ratio used before going to fingers or Multiples before seeing a voltage drop over the gate length. For example, I have always used the 10X rule, therefore if my L =100nm the max W could be 1um. If I drive the transistor gate from both ends, I would max out at W = 2um.

Just wondering, is this too relaxed. What is the max you guys recommend?

JGK

It's a good rule of thumb, I think. For critical timing one could try and estimate an RC time constant in comparison to required switching times. Anyway the models usually set a limit to max. (and min.) W/L ratios (because of model (in)accuracy, beyond).

Hello Erikl,

Thanks for the feedback. I have read somewhere that its a good rule of thumb. But wasn't sure. As for the models, they will let me make a 100X W to L ratio... which I think is really weird... I wonder if they put that always in the pdk on newer technologies.

JGK

jgk2004 said:

As for the models, they will let me make a 100X W to L ratio... which I think is really weird.

Click to expand...

Hello John,

I don't think this is weird if the model accuracy and all the routing RCs allow for. At least you can achieve a good power dissipation distribution per area.
But I've never used a process which allowed for a W/L > 20 (for the guaranteed model accuracy).

erikl

jgk2004 said:

Hello all,

I was wondering from the experienced guys, what the max recommend W to L ratio used before going to fingers or Multiples before seeing a voltage drop over the gate length. For example, I have always used the 10X rule, therefore if my L =100nm the max W could be 1um. If I drive the transistor gate from both ends, I would max out at W = 2um.

Just wondering, is this too relaxed. What is the max you guys recommend?

JGK

Click to expand...

If you are talking about a dynamic voltage drop, during transistor switching (and thus - about switching delay), then the proper metric is an effective gate resistance seen from the gate port.
For a one-sided contacted gate, the effective gate resistance is 1/3*Rg (Rg is an end-to-end resistance of gate poly), and that of a two-sided contacted gate is 1/12*Rg (additional factor of 1/2 is due to the fact that the current flowing through the gate contact from each side is 1/2 of the total gate current value).

Thus, you can safely increase the gate width four times (not two times), if you switch form one-sided contact layout to two-sided.

There is an additional parasitic effect in wide gates - a voltage drop on source/drain metal1, if layout is not designed properly.

Very wide gates (W>100 um) are widely used in power transistors.

Max
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Thanks for the feedback Timof, and catch I was missing the 1/2 since driving at both ends thanks.

JGK