Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

To keep ICG at high level of clock tree, any better way to fix "EN" setup violcation?

Status
Not open for further replies.
C

chris_li

Member level 2
Joined
Nov 7, 2005
Messages
42
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,569
To keep ICG at high level of clock tree, any better way to fix "EN" setup violcation?

Hi Guys, as you know, placing ICG clock gate cell at higher level as possible in clock tree, the better for power saving. However, it might introduce setup violation of "enable" pin of ICG. May I have you good suggestion how to kill two birds with one stone？

Many thanks.
 

Re: To keep ICG at high level of clock tree, any better way to fix "EN" setup violcat

chris_li said:
Hi Guys, as you know, placing ICG clock gate cell at higher level as possible in clock tree, the better for power saving. However, it might introduce setup violation of "enable" pin of ICG. May I have you good suggestion how to kill two birds with one stone？

Many thanks.
Click to expand...

Yes, two birds with one stone, make the tool aware of the clock skew at the Clockgate before CTS, this will drive ideal mode optimization to work harder ie. as much as it needs to, to meet timing.
Hope it helps,

Regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top