vjabagch
Member level 1
I have tried generating the conditions for my case statement using a generate, endgenerate block and I am unable to get it syntactically correct. Is my intended usage of generate supported by Verilog and what, if any, changes are needed to make it compile correctly.
Ignore the lack of brackets around the 10:0 because I could not insert the proper brackets without having them converted to html codes. My knowledge of bbcode is a bit basic.
The generate code:
Snippet of the desired output from elaboration.
Please advise.
Ignore the lack of brackets around the 10:0 because I could not insert the proper brackets without having them converted to html codes. My knowledge of bbcode is a bit basic.
The generate code:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 real a; real sin; real pi = 3.141592653589793238462643383279; task angle; //Ignore the lack of brackets here, it was done intentionaly //Original source code has proper square brackets input reg 10:0 index; output real angle; begin case (index) //Create the case statement generate genvar caseIndex; for (caseIndex = 0; caseIndex < 1024; caseIndex=caseIndex+1) begin caseIndex: angle = 2*pi*caseIndex/1024; end endgenerate endcase end endtask
Snippet of the desired output from elaboration.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 case (index) 10'd0: angle = 0; 10'd1: angle = 0.00613592315154256; 10'd2: angle = 0.0122718463030851; 10'd3: angle = 0.0184077694546277; 10'd4: angle = 0.0245436926061703; 10'd5: angle = 0.0306796157577128; 10'd6: angle = 0.0368155389092554; 10'd7: angle = 0.042951462060798; 10'd8: angle = 0.0490873852123405; 10'd9: angle = 0.0552233083638831; 10'd10: angle = 0.0613592315154256; 10'd11: angle = 0.0674951546669682; 10'd12: angle = 0.0736310778185108; 10'd13: angle = 0.0797670009700533; 10'd14: angle = 0.0859029241215959; 10'd15: angle = 0.0920388472731385; 10'd16: angle = 0.098174770424681; 10'd17: angle = 0.104310693576224;
Please advise.
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