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Help me find an error in Verilog code

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Flurkje

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What am I doing wrong?

I'm new to Verilog. For several weeks now, I'm trying to solve a problem, but I have no clue anymore so I try this forum. I already simplified the problem to the following code:

Code:
always @(posedge VSync or negedge HSync)
	if (HSync == 0)
		CounterLoc <= CounterLoc + 1;
	else
		CounterLoc <= 0;

Gives as a result that CounterLoc keeps counting and counting as long as HSync remains low (and not only once on the negedge as I would expect). Is this normal behavior?


Many thanks for your help.

David

FYI this is the complete module, any other remarks are also welcome:

Code:
module CounterModule(
    input Clock,
    input VSync,
    input HSync,
    input Comparator,
	 output reg [11:0] Distance,
	 output reg [11:0] Location,
	 output reg [11:0] CounterDist,
	 output reg [11:0] CounterLoc,
	 output reg [11:0] CurrentDist,
	 output reg [11:0] CurrentLoc
    );


always @(negedge HSync or posedge Clock )
	begin
		if (HSync == 0)
			CounterDist <= 0;
		else
			CounterDist <= CounterDist + 1;
	end

always @(negedge VSync)
		begin
					Distance <= CurrentDist;
					Location <= CurrentLoc;
		end



always @(posedge Comparator or posedge VSync or negedge HSync)


		begin
			
			if (HSync == 0)
				CounterLoc <= CounterLoc + 1;
			else
				begin
					if (Comparator == 1)
						begin
							if (CounterDist < CurrentDist)
								begin
									CurrentDist <= CounterDist;
									CurrentLoc <= CounterLoc;
								end
						end
					else
						begin
							CurrentDist <= 1023;
							CounterLoc <= 0;
						end
				end
		end


			
endmodule
 

Re: What am I doing wrong?

I think, you didn't yet understand the Verilog Syntax for synchronous always blocks. By specifying if (Hysnc == 0),
Hsync is marked as an asynchronous condition, while Vsync is an synchronous trigger. Verilog requires the negedge operator
with Hsync, but it's operation isn't actually edge sensitive. If you imagine the related hardware, Vsync is a clock input and
Hysnc is an asynchronous preload. It can't be used to count events. Exchanging the input events forms a regular counter with
VSync as an asynchronous reset.
Code:
always @(posedge VSync or negedge HSync) 
   if (VSync == 1) 
      CounterLoc <= 0;
   else 
      CounterLoc <= CounterLoc + 1;
 

    Flurkje

    Points: 2
    Helpful Answer Positive Rating
Re: What am I doing wrong?

Thank you very much for your reply.

I'm all confused now. So an always block is synchronous but the == condition is asynchronous right? Does that imply that this part will always be executed when the condition is true, even when the actual trigger from the sensitivity list is not triggered?

That would indeed explain what I'm experiencing, but that leaves me without a clue on how to solve my problem. Because that means that I can only use one edge 'trigger' per always statement, correct? And I can't use multiple always blocks for the same parameter(s) right?

Does that mean that the following requirement cannot be met with Verilog:
- Increase CounterLoc when HSync goes from High to low
- reset CurrentDist and CounterLoc when Vsync goes from Low to High
- store CounterDist in CurrentDist and CounterLoc in CurrentLoc when Comparator goes from high to Low.

Or is there another approach to solving this?

Many thanks,

David
 

Re: What am I doing wrong?

I got it working now:

Code:
always @(posedge Comparator or negedge VSync or negedge HSync) 


      begin 
          
         if (VSync == 0)
           begin
            CurrentDist <= 1023; 
            CounterLoc <= 0;  
           end
         else 
            begin 
               if (Comparator == 1) 
                  begin 
                     if (CounterDist < CurrentDist) 
                        begin 
                           CurrentDist <= CounterDist; 
                           CurrentLoc <= CounterLoc; 
                        end 
                  end 
               else 
                  begin 
                     CounterLoc <= CounterLoc + 1; 
                  end 
            end 
      end

I suppose the right approach is to look for the reset signals and use them correctly rather than just writing if statements? It seems that knowledge of the underlaying hardware is more important here than it is with other programming languages.

Thanks,

David
 

Re: What am I doing wrong?

Because that means that I can only use one edge 'trigger' per always statement, correct?
Exactly, because the D-FlipFlops representing the code have only one clock input.
It seems that knowledge of the underlaying hardware is more important here than it is with other programming languages.
Very true.
 

    Flurkje

    Points: 2
    Helpful Answer Positive Rating
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