lokesh garg
Member level 5
in cadence i m using umc 180nm technology labrary?can anybody tell me which fabrication tech we are using either nwell/pwell or we are using twin-well process.... plz reply
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Right.lokesh garg said:i think its using nwell process i m saying it because when i select nmos from pdk we did not get any well for nmos.
Ask the foundry.lokesh garg said:tell me how can i switch to twin well process.
Of course.lokesh garg said:do i need to change whole library which use twin well process????
No, the type of process never ever is the reason for an unintended short-circuit between nodes. This can only result from layout generation, either created by automatic or by human action.lokesh garg said:in one of the post here i read that i m using nwell procell which have same substrate thats why its showing connection between ground and vout.
bellona indicated a possible reason (pcell flattening before layout creation).lokesh garg said:plz tell me what is the reason behind it...... thanks
lokesh garg said:i think its using nwell process i m saying it because when i select nmos from pdk we did not get any well for nmos. tell me how can i switch to twin well process. do i need to change whole library which use twin well process????
lokesh garg said:can u tell me how to access T-well option, i have MM/RF kit...
lokesh garg said:i m having a prb, my lyaout still have incomplete nets may be i m missing something, can anybody tell me how to connect N+ poly resistor in layout, i m attaching may schematic and layout of resistor that i m using
lokesh garg said:in my layout its still saying there are two incomplete nets
Lokesh,wpchan05 said:... you need sub contact for the n-well.