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100 MHz can affect the circuit operation ?

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Vonn

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Hi all ,
Iam designing a board working in a telecommunication field
this board have FPGA and PPC . I had to use 100MHz clock for the
FPGA ...
1- Does this frequency can affect any track passing in the same position
but in another layer
2- Does this frequency can affect a near track carrying a voice channel
3- How can I protect the affection caused by this frequency ,if any,
should I surrounded this track by a ground track ? or empty the
power polygons in the other layers in the same position ?
Thanks
 

Hi,
At this freq, you should use controlled impedance traces, to avoid signal reflections. Of couse, surrounding traces can be affected by this clock. Using coplanar waveguides method for controlled impedance traces will minimise interferences between closed high speed traces. Also, you should use at least 4 layer board, 2signal+1gnd plane+1 power plane. Also, you should separate analog and digital planes. Further, if your design is industrial, you should be concerned of issues like EMI reduction, ESD protection. You can find helpfull information at "e-book upload/download"
 

Hi.
At this frequency Seperating of Analog and Digital circuits is necessary.
Note that Digital and Analog grounds must be conectted only at one point.
Also if you can not implement your desing in more than 2 layer board, then you can use ground track for reducing leakage.
in this design any high frequency line is placed beetween two ground line.
Bests.
 

The higher harmonics of the clock can post problems to your board if you never take care of the clock trace. Try to route this signal on a single layer. The ground return current of the clock run directly beneath the signal trace (if there is a ground plane below the clock). Try to keep the ground plane layer intact, if you could afford
 

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