help on putting this vhdl code working

I NEED SOME HELP TO PUT THIS CODE WORKING. PLEASE!! IF EN='0' then O="0000" else O(x)=y...etc

library IEEE;
use IEEE.std_logic_1164.all;

entity MAIN is

port(
A : in std_logic_vector(0 to 3);
B : in std_logic_vector(0 to 3);
C : in std_logic_vector(0 to 3);
D : in std_logic_vector(0 to 3);
E : in std_logic_vector(0 to 3);
F : in std_logic_vector(0 to 3);
G : in std_logic_vector(0 to 3);
H : in std_logic_vector(0 to 3);
EN : in std_logic;
O : out std_logic_vector(0 to 3)
);

end MAIN;


architecture arch1 of MAIN is

begin

reset: process(EN)
begin
if EN='0' then
O<= "0000";
end if;
end process reset;

O(0) <= '1' when (A=E) or (A=F) or (A=G) or (A=H) else '0';
O(1) <= '1' when (B=E) or (B=F) or (B=G) or (B=H) else '0';
O(2) <= '1' when (C=E) or (D=F) or (E=G) or (F=H) else '0';
O(3) <= '1' when (A=E) or (A=F) or (A=G) or (A=H) else '0';

end arch1;

THE ERROR : Error 554 line 34 : Some bits of signal 'o' are driven more than once
HOW I make a simple if(EN==0){O="0000"} else{O(0)=x , y, etc..} like in Java or C?

Thank you
Flavio Silvestre

You didn't tell the error message, but something like "multiple drivers for net O[x]" can be expected.

The main logic in your design is of asynchronous type, pure combinational. It doesn't need a Reset input cause it's memoryless, doesn't depent on previous states. The En input can be used in the combinational outputs, with priority, if necessary, e. g.:

Generally, assignments to a signal can be made only in one place in concurrent code (outside processes). If the assignment is in a process, than you can have multiple assignments, the last wins.

It should be noticed, that the comparator realised in the code most likely shows glitches at the output when the inputs are changing. This would also happen with dedicated logic IC of similar function. In usual synchronous HDL designs, there is a place, where the compare result would be sampled by a system clock at a moment when it's not expected to change.

frs89 said:

O(0) <= '1' when (A=E) or (A=F) or (A=G) or (A=H) else '0';
O(1) <= '1' when (B=E) or (B=F) or (B=G) or (B=H) else '0';
O(2) <= '1' when (C=E) or (D=F) or (E=G) or (F=H) else '0';
O(3) <= '1' when (A=E) or (A=F) or (A=G) or (A=H) else '0';

Click to expand...

Put these lines inside 1 process, it will work. With those branching instruction like Case, When, If you have to put inside "process" .

Put these lines inside 1 process.

Click to expand...

You didn't try! Conditional assignment syntax isn't applicable in a process. You would have to use IF statements instead.

Those stuffs i have archived practically, those CASE- WHEN-IF must be put inside process.
regarding :

FvM said:

Conditional assignment syntax isn't applicable in a process

Click to expand...

Sorry i dont believe it ... Nice weekend.

IEEE 1076 explain this topic at great length.

For a given conditional signal assignment, there is an equivalent process statement corresponding to it as defined for any concurrent signal assignment statement. If the conditional signal assignment is of the form

target <= options
waveform1 when condition1 else
waveform2 when condition2 else
• • •
waveformN–1 when conditionN–1 else
waveformN when conditionN;

then the signal transform in the corresponding process statement is of the form

if condition1 then
wave_transform1
elsif condition2 then
wave_transform2
• • •
elsif conditionN–1 then
wave_transformN–1
elsif conditionN then
wave_transformN
end if ;

Click to expand...

Sorry for my mistakes and laziness FvM...
I have tried and i got that code work fine :

xxx said:

entity MAIN is

port(
A : in std_logic_vector(0 to 3);
B : in std_logic_vector(0 to 3);
C : in std_logic_vector(0 to 3);
D : in std_logic_vector(0 to 3);
E : in std_logic_vector(0 to 3);
F : in std_logic_vector(0 to 3);
G : in std_logic_vector(0 to 3);
H : in std_logic_vector(0 to 3);
EN : in std_logic;
O : out std_logic_vector(0 to 3)
);

end MAIN;


architecture arch1 of MAIN is

begin

reset: process(EN)
begin
if EN='0' then
O<= "0000";
end if;
if (EN='1') and ((A=E) or (A=F) or (A=G) or (A=H)) then O(0)<='1' ;
else O(0)<='0';
end if;
if (EN='1') and ((B=E) or (B=F) or (B=G) or (B=H)) then O(1)<='1' ;
else O(1)<='0'; end if;
if (EN='1') and ((C=E) or (D=F) or (E=G) or (F=H)) then O(2)<='1' ;
else O(2)<='0'; end if;
if (EN='1') and ((A=E) or (A=F) or (A=G) or (A=H)) then O(3)<='1' ;
else O(3)<='0'; end if;
end process reset;

end arch1;

Click to expand...

I have merge the 2 posible process into 1 to avoid the possibility of multi source error. Because it is not necessary to make a seperate Reset process...
Secondly , those case-when -if i'm taliking about was CASE-WHEN (in 1) and IF. But not When (alone) ... That may cause misunderstood...

Yes, case statements can be used only in a process.

Your process if then variant is functional equivalent to the conditional assignment variant i suggested in my first posting. Both can be used.

However one point should to be corrected in your code: All inputs A-H have to included in the process sensitivity list, otherwise the HDL compiler is free to ignore changes at these inputs, although I wouldn't expect it in this case.