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communication PowePC FPGA

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eiria

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Hello everybody.
I'm studying the viability of using pattern matching on an FPGA.
My VHDL code runs ok in Simulation: it takes characters from a file.
I need to execute this into an FPGA and communicating with the PowerPC, but I don't know how to take characaters from the file.
Anyone can help me, please?
Thanks a lot.


Ariadna
 

Most likely, the FPGA would have a data bus towards the processor.
 

Thanks FvM

How could I open this data bus from a C program? I'll explain better what I need: I have to run a C code which would read chars from a file and then send them to the FPGA, and read the FPGA output.
Any link or tutorial will be appreciated.
Thanks,


Ariadna
 

I don't know a particular tutorial, I just can say that creating bus interfaces similar to a processor peripheral or a memory device in FPGAs is an obvious technique. I have used it since working with FPGA in signal processing applications. Depending on the required throughput, also a SPI or I2C slave interface could be an option. You can define an adress space as needed.

FPGA internal memory may be directly mapped to the interface, probably organized as dual port RAM, one port at the bus and one for internal access. From the processor's view, the FPGA interface looks like any peripheral at the bus. Some considerations are necessary in adapting the interface timing to processor needs, wait states may be required to perform a read access from FPGA resources (e. g. internal RAM) that are operating from a synchronous clock.

The first step would be in any case to define the control and data interface required by the application. If it involves a large data storage capacity that exceeds FPGA internal resources, external memory can be connected to the FPGA, it can be also mapped transparently to the databus.
 

Thanks FvM.

I'll try it.
I'm a student at the University and I didn't know nothing about FPGA, before. It's my first experience on it.
I appreciate your help.


Ariadna
 

If your project includes design of a processor interface in FPGA, I'm confident that you are able realize it. Nearly everything can be done with FPGA. Other EDAboard members and I surely can give some help on the way. I would expect however, that your project has also responsible support from your university. In particular, it should help in deciding what's an appropriate effort for an individual project part, e. g. the interface design.

If your work isn't part of an official study project but free activity, you're invited to ask for help anyway.
 

Using FIFOs and asynchronous IO's may be advisable to maximize throughput for some applications, but not generally, to my opinion.
 

Thanks for help me.

Do you know any tutorial to configure the USB-connection XUP Virtex-2Pro in Linux? I'm trying to download the bitstream but this is the result:

Cable Type = 3, Revision = 0.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1030.

CPLD file version = 0012h.
CPLD version = 0012h.
Identifying chain contents ....
usb_transfer: -110 (No error)
read count != nBytes, rc = FFFFFF92.
read failed FFFFFF92.
'1': : Manufacturer's ID =Unknown

INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.

Thanks!



Ariadna
 

I think you can install the linux OS on the PowerPC CPU. And the FPGA can be used to realize the "machine pattern" part as a accelator engine.
 

Hi all.
Thanks for all your comments, you've been of great help.

Now I'm stuck again with the communication.

I already know how to establish a FIFO connection between the PPC and the FPGA, but it seems it's not working.

I have this piece of C code:

Code: 
char * pattern = "ab";
char * text = "abcdef";
  
for (i = 0; i < 2; i++) {
	input = 0x00000000;
	temp =  input | pattern[i];
	xil_printf("%X\n\r",temp);
	MY_PATTERN_mWriteToFIFO(baseaddr, temp);
}

for (i = 0; i < 6; i++) {
	input = 0x00000000;
	temp =  input | text[i];
	xil_printf("%X\n\r",temp);
	MY_PATTERN_mWriteToFIFO(baseaddr, temp);
}

xil_printf("Testing read...\n\r");
while (!MY_PATTERN_mReadFIFOEmpty(baseaddr)) {
	temp = MY_PATTERN_mReadFromFIFO(baseaddr);
	xil_printf("Read:  0x%x \n\r", temp);
}
xil_printf("Done.\n\r");

And in the VHDL:

Code: 
entity pattern is 
port ( 	
			clock : in std_logic;
			input : in std_logic_vector(0 to 7);
			mk : out std_logic_vector (0 to 31)
			);
end pattern;

-- How do I the read **HERE** the input char by char from the FIFO??

-- VHDL CODE THAT PROCESSES THE INPUT

-- How do I return an integer through the FIFO **HERE**?

The problem now is that I can't check if the programs are communicating properly since I'm only getting zeroes when reading from the FIFO.

If you need any more code please ask for it.

Thanks for your help.

Ariadna.
 

I think you only have the basic idea how the "C" program interface with the FPGA. You should learn further to understand the following things:
1. How can you C program be compiled to be runnable on the CPU?
2. What's the bus interface between the FPGA and the CPU?
3. Depend on the bus information, you can decide how can the data be transferred between the "CPU" and "FPGA". Usually, there are two modes can be used: PIO(programable IO) and DMA(Direct Memory Access).
4. When the data can be received by the FPGA, you can design the internal logic to realize your pattern matching.
 

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