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[SOLVED] VHDL code for serial in parallel out needed

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dimitarlazarevski

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Could any one provide me the code for serial in parallel out. It has to have 6 bit out data. The serial in data i have to put it by my hand in binary code. The board is Xilinx Spartan 3E; chipset? XC3S100E; TQ144

BASYS (Basic System Board) Digilent
Thank u
 

Re: vhdl code needed...

A basic serial-to-parallel conversion is just a few lines of code. There may be other requirements you didn't yet tell.
Code: 
signal sr: std_logic_vector(5 downto 0);
begin
process (clk);
  begin
    if rising_edge(clk) then
      begin
        sr <= sr(4 downto 0) & si;
      end;
  end;
end;
 

Re: vhdl code needed...

Hi,

Just some enhancments :

Code: 
signal sr: std_logic_vector(5 downto 0);
...

begin
...
 
process (clk, rst); 
begin 

    if rst = '0' then
      sr <= (others <= '0');

    elsif rising_edge(clk) then 
      sr <= sr(4 downto 0) & si; 

    endif; 

end;
 

vhdl code needed...

I think you can use inbuilt serdes blocks(soft-blocks) for this .You can take the primitive definition from Xilinx data sheet .
 

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