chronos04
Newbie level 1
abstract on camera link camera interface
Hello,
I've implemented a camera link deserializer interface based on a virtex 4 FPGA (using ML402 development board). I'm using the LVDS 2.5 V inputs of the board and a cable with one end open.
The module works fine when i use a short cable. However, my application needs to use a long cable (with a discontinuity) which doesn't work so fine. The thing is that I guess there is a match problem in the board reception side, because when i represent the eye diagram of the incoming signals (once it's converted to LVTTL) and the long cable is used, it's really bad.
I know that it is possible to use this long cable because it works with a generic frame grabber.
I've tried using the DCI (Digital Control impedance) of the FPGA, LVDS_EXT standard... but i don't reach a solution...
If someone could have some experience in this field...
Thank very much in advace !
Hello,
I've implemented a camera link deserializer interface based on a virtex 4 FPGA (using ML402 development board). I'm using the LVDS 2.5 V inputs of the board and a cable with one end open.
The module works fine when i use a short cable. However, my application needs to use a long cable (with a discontinuity) which doesn't work so fine. The thing is that I guess there is a match problem in the board reception side, because when i represent the eye diagram of the incoming signals (once it's converted to LVTTL) and the long cable is used, it's really bad.
I know that it is possible to use this long cable because it works with a generic frame grabber.
I've tried using the DCI (Digital Control impedance) of the FPGA, LVDS_EXT standard... but i don't reach a solution...
If someone could have some experience in this field...
Thank very much in advace !
