zhiling0229
Member level 1
Hi guys,
I need your help. I'm actually working on isolating a failure on an FPGA.
From the electrical analysis I was able to identified the failure was caused by a driver or a multiplexer (Circuit.jpg) which was stuck logic 0 instead of driving a 1.
I was able to disable the driver. In hope that when I transmit from another driver which shares the same line it did not pull to zero.
However I could not conclude that the driver is ok as the line connecting to the share line is quite far. I'm not sure a minor bridging to vss near the problematic driver might not be seen at it might be the buffer as the drivers were powerful enough to overcome the minor bridging.
Is there any other way which I can perform to isolate whether it is a multiplexer or a driver fault.
the whole design for the particular area range from diffusion, poly, metal 1 until 5.
Please anyone, can you give me some ideas how to proceed. Kind of desprate here.
I need your help. I'm actually working on isolating a failure on an FPGA.
From the electrical analysis I was able to identified the failure was caused by a driver or a multiplexer (Circuit.jpg) which was stuck logic 0 instead of driving a 1.
I was able to disable the driver. In hope that when I transmit from another driver which shares the same line it did not pull to zero.
However I could not conclude that the driver is ok as the line connecting to the share line is quite far. I'm not sure a minor bridging to vss near the problematic driver might not be seen at it might be the buffer as the drivers were powerful enough to overcome the minor bridging.
Is there any other way which I can perform to isolate whether it is a multiplexer or a driver fault.
the whole design for the particular area range from diffusion, poly, metal 1 until 5.
Please anyone, can you give me some ideas how to proceed. Kind of desprate here.