hoheiho
Newbie level 2
Hi all,
I am using a low cost FPGA (EP2C5T144C6) and trying to compile my verilog code in Quartus II.
The error message come out:
Error (170011): Design contains 5204 blocks of type combinational node. However, device contains only 4608.
I have try to reduce some If,Else case but it has no big different. Is there any suggestions that i can try to solve this problem??
Thanks
I am using a low cost FPGA (EP2C5T144C6) and trying to compile my verilog code in Quartus II.
The error message come out:
Error (170011): Design contains 5204 blocks of type combinational node. However, device contains only 4608.
I have try to reduce some If,Else case but it has no big different. Is there any suggestions that i can try to solve this problem??
Thanks