quyleanh
Member level 3
I'm creating some Standard Cells: NOT, NAND, NOR... with fix parametters. For size optimization, I plan to recreate the NMOS and PMOS cell as design rule from PDK.
I have noticed that the Poly gate layer is longer than Select layer in default PCell. In my customization, the height of Poly gate is shorter than default.
I did check the DRC, LVS, ERC. Everything is OK. But I still do not know why the default has longer. Could anyone please explain it? Thank you very much.
I have noticed that the Poly gate layer is longer than Select layer in default PCell. In my customization, the height of Poly gate is shorter than default.
I did check the DRC, LVS, ERC. Everything is OK. But I still do not know why the default has longer. Could anyone please explain it? Thank you very much.