kurax
Newbie level 4
My Synthesis Script,
This is the script I use to synthesize my design file. My question is, I want to use multiple library files. Say tech1.lib, tech2.lib, etc. Use the synthesis tool to take in all of them and do synthesis for each and every one of them and generate reports. And if possible the synthesis tools should automatically say which library best matches the timing.
Thanks in advance.
Code:
#Setting Library and Design Path
set_attribute lib_search_path ../lib/
set_attribute hdl_search_path ../design_files/
#Setting Library and Design Files
set_attribute library tech.lib
#Analyze and Elaborate the Design File
read_hdl -sv counter.sv
elaborate
# Apply Constraints and generate clocks
read_sdc ../constraints/constraints.sdc
# Synthesize the design to the target library
synthesize -to_mapped -effort medium
# Write out the reports
report timing > counter_timing.rep
report gates > counter_cell.rep
report power > counter_power.rep
# Write out the structural Verilog and sdc files
write_hdl > counter_netlist.v
write_sdc > counter_sdc.sdc
This is the script I use to synthesize my design file. My question is, I want to use multiple library files. Say tech1.lib, tech2.lib, etc. Use the synthesis tool to take in all of them and do synthesis for each and every one of them and generate reports. And if possible the synthesis tools should automatically say which library best matches the timing.
Thanks in advance.