mahmood.n
Member level 5
Using Quartus 12, I would like to know why
won't synthesize to a double edge (raise and fall) flip flop? I get this error
Also, when I wrote
in active-hdl the functional simulation shows a double edge flip flop as below
but quartus shows the following error
I know that is related to synthesis templates that tools use. I would like to know which one is closer to standard.
Code:
wait until ((clk'event and clk ='1') or (clk'event and clk ='0'));
Code:
Error (10628): VHDL error at test3.vhd(9): can't implement register for two clock edges combined with a binary operator
Error (10658): VHDL Operator error at test3.vhd(9): failed to evaluate call to operator ""or""
Code:
wait on clk;
but quartus shows the following error
Code:
Error (10533): VHDL Wait Statement error at test3.vhd(10): Wait Statement must contain condition clause with UNTIL keyword
I know that is related to synthesis templates that tools use. I would like to know which one is closer to standard.