Alexxk
Junior Member level 3
Hi!
Today I encoutered a problem when porting a digital block design from innovus to virtuoso:
I extracted the netlist from Innovus with save netlist aswell as the DEF and imported them to virtuoso.
During LVS in virtuoso I discovered that all of the Flip-Flops with reset (the synthesis tool seems to take them in around 10% of the cases a FF is needed, I guess because of the timing), don't have their reset pin connected (the design is pipelined and needs to be flushed anyway) and should be connected to vdd.
So I checked the netlist generated during synthesis (cadence genus) and there the pin should be connected to 1'b1. The netlist I extracted from Innolvus after timing signoff, also has it tied to 1'b1.
But when I look into the design browser of innovus, the pins are connected to 0x0. But it seems that doesnt mean it should be connected to VSS....
I think I could solve all of this by redoing my design with a reset and tying it to vdd externally, but I think this behaviour is very strange, especially because the extracted verilog netlist shows the connections while in innovus design browser they are not there.
Thank you for your help!
Today I encoutered a problem when porting a digital block design from innovus to virtuoso:
I extracted the netlist from Innovus with save netlist aswell as the DEF and imported them to virtuoso.
During LVS in virtuoso I discovered that all of the Flip-Flops with reset (the synthesis tool seems to take them in around 10% of the cases a FF is needed, I guess because of the timing), don't have their reset pin connected (the design is pipelined and needs to be flushed anyway) and should be connected to vdd.
So I checked the netlist generated during synthesis (cadence genus) and there the pin should be connected to 1'b1. The netlist I extracted from Innolvus after timing signoff, also has it tied to 1'b1.
But when I look into the design browser of innovus, the pins are connected to 0x0. But it seems that doesnt mean it should be connected to VSS....
I think I could solve all of this by redoing my design with a reset and tying it to vdd externally, but I think this behaviour is very strange, especially because the extracted verilog netlist shows the connections while in innovus design browser they are not there.
Thank you for your help!