liletian
Full Member level 6
Hi All
For the digital computer, there always has a halt mode which basically mean to turn off the system.
In the verilog, a $finish is used in verilog code.
I am just wondering how the synthesizer will synthesize this to?
Thanks
Brian
For the digital computer, there always has a halt mode which basically mean to turn off the system.
In the verilog, a $finish is used in verilog code.
I am just wondering how the synthesizer will synthesize this to?
Thanks
Brian