ebuddy
Full Member level 3
Hi,
It is a common practice to have separate SDC constraint files for functional mode and scan mode during ASIC synthesis and static timing analysis.
Just curious why that is the case? So in scan mode SDC, we need to do :
1. create_clock for scan clock; this scan clock usually has low frequency than the function clock
2. set_input_delay and set_output_delay for scan_in, scan_out, scan_en.
3. set_case_analysis to enable scan_mode
Is it because we have the set_case_analysis and we have to put that in a separate SDC file?
Any comments?
Regards,
ebuddy
It is a common practice to have separate SDC constraint files for functional mode and scan mode during ASIC synthesis and static timing analysis.
Just curious why that is the case? So in scan mode SDC, we need to do :
1. create_clock for scan clock; this scan clock usually has low frequency than the function clock
2. set_input_delay and set_output_delay for scan_in, scan_out, scan_en.
3. set_case_analysis to enable scan_mode
Is it because we have the set_case_analysis and we have to put that in a separate SDC file?
Any comments?
Regards,
ebuddy