Yorki
Newbie level 3
Hello there,
I'm using the 10M08SCE144A7G FPGA.
In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (signal PLL_L_CLKOUTp of the FPGA) to give the clock to these 3 converters.
There is only 1 output of this type with this FPGA.
I'll like to know if there is any recommendations using this output signal to fed 3 diferents Analog to Digital Converters ? (fanout , layout for exemple)
Is this a good way to do it ?
Maybe driving the PLL output to 3 diferents standard fast I/O pins (1 pin for 1 DAC) is a better design ?
Thank you for your help.
Julien.
I'm using the 10M08SCE144A7G FPGA.
In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (signal PLL_L_CLKOUTp of the FPGA) to give the clock to these 3 converters.
There is only 1 output of this type with this FPGA.
I'll like to know if there is any recommendations using this output signal to fed 3 diferents Analog to Digital Converters ? (fanout , layout for exemple)
Is this a good way to do it ?
Maybe driving the PLL output to 3 diferents standard fast I/O pins (1 pin for 1 DAC) is a better design ?
Thank you for your help.
Julien.