moro
Member level 3
Hello all,
i started out a uart tx module for sending a packet of 4bytes ( one at a time).... the data is sent ok, but i am facing some strange behaviour
My problem is on the enable signal, i hooked the enable of the uart module to a button on my board, also connected a LED in the logic to have a "visible feel"
If i press the button once, i expect some uart action, but if i release the button the uart should be stoped... but its not....
the LED is lighted and with a logic analyzer i have continous data when the button is not pressed !!
Its like the enable input remains latched in Hi state... and i wonder why? Is there a problem in my code? i did some simulation in ISE but there everything is working as expected
I highlighted the problem in my code bellow
here is my top module
and my 32bit uart module
i started out a uart tx module for sending a packet of 4bytes ( one at a time).... the data is sent ok, but i am facing some strange behaviour
My problem is on the enable signal, i hooked the enable of the uart module to a button on my board, also connected a LED in the logic to have a "visible feel"
If i press the button once, i expect some uart action, but if i release the button the uart should be stoped... but its not....
the LED is lighted and with a logic analyzer i have continous data when the button is not pressed !!
Its like the enable input remains latched in Hi state... and i wonder why? Is there a problem in my code? i did some simulation in ISE but there everything is working as expected
I highlighted the problem in my code bellow
here is my top module
Code:
module main_module(
output uart_out , // uart tx line
input clk,
input button,
output LD2
);
parameter [31:0] testing = 32'h 44332211;
// instatiate the uart module
uart4byte uuu(
.uart_clock(clk),
.data(testing),
.enable(button),
.tx_out(uart_out),
.led(LD2) // output to led
);
endmodule;
and my 32bit uart module
Code:
module uart4byte(
input uart_clock,
input [31:0] data,
[COLOR="#FF0000"]input enable, [/COLOR]
output reg tx_out,
output reg led
);
parameter idle = 3'b000; // 0
parameter start = 3'b001; // 1
parameter stop = 3'b010; // 2
parameter send = 3'b011; // 3
parameter clear = 3'b100; // 4
reg [7:0] pos = 0;
reg [7:0] ii = 0;
reg [7:0] state =0; // set initial 3bit register to 0value ( binary 000) ( idle)
reg [7:0] index =0; // bit index
initial begin
tx_out = 1;
end
always @(posedge uart_clock) begin
case (state)
idle:
begin
tx_out <=1'b1; // in idle the dataline is set to high
index <=0; // reset bit index
[COLOR="#FF0000"] if(enable == 1) begin
state <= start; // set state for start(1)
led<=1;
end
else begin
state <=idle;
led<=0;
end[/COLOR]
end
start: // 1
begin
tx_out <=1'b0; // set dataline to low, this indicates start bit in uart communication
state <= send; // set next state for sending the 8bit data
end
send: //3
begin
tx_out <= data[index+pos];
if(index < 7) begin // check to see if we sent all 8 data bits
index <= index +1;//increment by 1
state <= send; // set next state for sending remaining bits
end
else begin // if we sent all the data bits do this...
index <=0 ; // clear the index counter
state <= stop; // set next state for sending the stop bit
end
end
stop:
begin
tx_out<=1'b1; // set the dataline to high, indicating a stop bit
state <= clear; // set next state for clearing the data line
end
clear:
begin
tx_out<=1'b1; // set the dataline to high, indicating a stop bit
if((index+pos)== 31) begin
pos<=0;
state <= idle; // set next state for clearing the data line
end
else begin
state<=start; // back to start
pos <=pos + 8; // increment by 8positions
end
end
default:
state <= idle;
endcase
end
endmodule